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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT9015 Nine wide Schmitt trigger buffer/line driver
Product specification Supersedes data of March 1988 File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
Nine wide Schmitt trigger buffer/line driver
FEATURES * Schmitt trigger action on all data inputs * Output capability: standard * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT9015 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns
74HC/HCT9015
The 74HC/HCT9015 are nine wide Schmitt trigger buffer/line drivers with Schmitt trigger inputs. These inputs transform slowly changing input signals into sharply defined jitter-free output signals. The "9015" is identical to the "9014" but has non-inverting inputs.
TYPICAL SYMBOL tPHL/ tPLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay An to Yn input capacitance power dissipation capacitance per buffer notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 12 3.5 30 HCT 13 3.5 32 ns pF pF UNIT
December 1990
2
Philips Semiconductors
Product specification
Nine wide Schmitt trigger buffer/line driver
PIN DESCRIPTION PIN NO. 1, 2, 3, 4, 5, 6, 7, 8, 9 10 19, 18, 17, 16, 15, 14, 13, 12, 11 20 SYMBOL A0 to A8 GND Y0 to Y8 VCC NAME AND FUNCTION data inputs ground (0 V) data outputs positive supply voltage
74HC/HCT9015
page
1
A0
Y0
page
19
1
19
2
A1
Y1
18
2
18
3
A2
Y2
17
3
17
4
A3
Y3
16
4
16
5
A4
Y4
15
5
15
6
A5
Y5
14
6
14
7
A6
Y6
13
7
13
8
A7
Y7
12
8
12
9
A8
Y8
MBA016
11
9
MBA013
11
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Nine wide Schmitt trigger buffer/line driver
74HC/HCT9015
handbook, halfpage
An
Yn
MBA017
Fig.4 Functional diagram.
Fig.5 Logic diagram (one Schmitt trigger).
FUNCTION TABLE INPUTS An L H Notes 1. H = HIGH voltage level L = LOW voltage level OUTPUTS Yn L H
December 1990
4
Philips Semiconductors
Product specification
Nine wide Schmitt trigger buffer/line driver
DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Transfer characteristics are given below. Output capability: standard ICC category: MSI TRANSFER CHARACTERISTICS FOR 74HC Voltages are referred to GND (ground = 0 V) Tamb (C) 74HC SYMBOL PARAMETER min. VT+ positive-going threshold 0.70 1.75 2.30 0.30 1.35 1.80 0.2 0.4 0.5 +25 -40 to +85 -40 to +125
74HC/HCT9015
TEST CONDITIONS UNIT V CC WAVEFORMS (V) V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Figs 6 and 7
typ. max. min. max. min. max. 1.13 1.50 2.37 3.15 3.11 4.20 0.70 1.10 1.80 2.40 2.43 3.30 0.43 0.80 0.57 1.00 0.68 1.10 0.70 1.75 2.30 0.30 1.35 1.80 0.18 0.40 0.50 1.50 3.15 4.20 1.10 2.40 3.30 0.80 1.00 1.10 0.70 1.75 2.30 0.30 1.35 1.80 0.15 0.40 0.50 1.50 3.15 4.20 1.10 2.40 3.30 0.80 1.00 1.10
VT-
negative-going threshold
V
Figs 6 and 7
VH
hysteresis (VT+ - VT-)
V
Fig.6
AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 -40 to +85 -40 to +125 max. 160 32 27 110 22 19 ns 2.0 4.5 6.0 2.0 4.5 6.0 Fig.8 UNIT V CC WAVEFORMS (V) TEST CONDITIONS
min. typ. max. min. tPHL/ tPLH propagation delay An to Yn output transition time 33 12 10 19 7 6 105 21 18 75 15 13
max. min. 130 26 22 95 19 16
tTHL/ tTLH
ns
Fig.8
December 1990
5
Philips Semiconductors
Product specification
Nine wide Schmitt trigger buffer/line driver
DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Transfer characteristics are given below. Output capability: standard ICC category: MSI
74HC/HCT9015
Note to HCT types The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT An UNIT LOAD COEFFICIENT 0.3
TRANSFER CHARACTERISTICS FOR 74HCT Voltages are referred to GND (ground = 0 V) Tamb (C) 74HCT SYMBOL PARAMETER min. VT+ VT- VH positive-going threshold negative-going threshold hysteresis (VT+ - VT-) 0.9 1.2 0.7 0.8 0.2 0.2 +25 -40 to +85 -40 to +125 UNIT V CC WAVEFORMS (V) 4.5 5.5 4.5 5.5 4.5 5.5 TEST CONDITIONS
typ. max. min. max. min. max. 1.50 2.0 1.70 2.1 1.06 1.4 1.27 1.7 0.44 0.8 0.44 0.8 0.9 1.2 0.7 0.8 0.2 0.2 2.0 2.1 1.4 1.7 0.8 0.8 0.9 1.2 0.7 0.8 0.2 0.2 2.0 2.1 1.4 2.7 0.8 0.8 V V V Figs 6 and 7 Figs 6 and 7 Figs 6 and 7
AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER +25 -40 to +85 -40 to +125 max. 48 22 ns ns 4.5 4.5 Fig.8 Fig.8 UNIT V CC WAVEFORMS (V) TEST CONDITIONS
min. typ. max. min. max. min. tPHL/ tPLH tTHL/ tTLH propagation delay An to Yn output transition time 18 7 32 15 40 19
December 1990
6
Philips Semiconductors
Product specification
Nine wide Schmitt trigger buffer/line driver
TRANSFER CHARACTERISTIC WAVEFORMS
74HC/HCT9015
handbook, halfpage
VO
MBA325
handbook, halfpage
VI
VT VT
V H
VH VT VT
VI
VO
MBA324
Fig.6 Transfer characteristic.
Fig.7
Waveforms showing the definition of VT+, VT- and VH.
AC WAVEFORMS
handbook, full pagewidth
A n INPUT
VM (1) t PLH
t
PHL
Yn OUTPUT t THL
VM (1) t TLH
MBA019
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the input (An) to output (Yn) propagation delays and the output transition times.
PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines".
December 1990
7

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